With an increase in size of a memory device, a bit line and a word line connected with a memory cell may have a hierarchical structure. For example, the bit line may include a global bit line and a plurality of local bit lines connected with the global bit line. The word line may include a main word line and a plurality of sub word lines connected with the main word line.
In such a case, a distance between a read circuit and the memory cell or a distance between a write circuit and the memory cell may be significantly increased. Therefore, capacitance of the bit line may also be relatively large. Further, the amount of current required for charging and discharging the bit line may also be relatively large. For example, a memory device in which hundreds of read circuits simultaneously operate may require current of hundreds of milliamps in order to charge a plurality of bit lines for each read operation. The current consumption may deteriorate current performance of a memory and generate power noise.
The global bit line may be divided into a write global bit line and a read global bit line. Herein, coupling noise may be generated in the read global bit line depending on a change in voltage level of the write global bit line.